Update project file.
[bos2k9.git] / bos2k9.qsf
1 # Copyright (C) 1991-2008 Altera Corporation
2 # Your use of Altera Corporation's design tools, logic functions 
3 # and other software and tools, and its AMPP partner logic 
4 # functions, and any output files from any of the foregoing 
5 # (including device programming or simulation files), and any 
6 # associated documentation or information are expressly subject 
7 # to the terms and conditions of the Altera Program License 
8 # Subscription Agreement, Altera MegaCore Function License 
9 # Agreement, or other applicable license agreement, including, 
10 # without limitation, that your use is for the sole purpose of 
11 # programming logic devices manufactured by Altera and sold by 
12 # Altera or its authorized distributors.  Please refer to the 
13 # applicable agreement for further details.
14
15
16 # The default values for assignments are stored in the file
17 #               bos2k9_assignment_defaults.qdf
18 # If this file doesn't exist, and for assignments not listed, see file
19 #               assignment_defaults.qdf
20
21 # Altera recommends that you do not modify this file. This
22 # file is updated automatically by the Quartus II software
23 # and any changes you make may be lost or overwritten.
24
25
26
27 # Project-Wide Assignments
28 # ========================
29 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
30 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:08:21  MAY 10, 2009"
31 set_global_assignment -name LAST_QUARTUS_VERSION 8.1
32 set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
33 set_global_assignment -name SMART_RECOMPILE ON
34 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
35 set_global_assignment -name VHDL_FILE fhw_sd/sd_host.vhd -library fhw_sd
36 set_global_assignment -name VHDL_FILE fhw_sd/sd_flow_e.vhd -library fhw_sd
37 set_global_assignment -name VHDL_FILE fhw_sd/sd_parser_e.vhd -library fhw_sd
38 set_global_assignment -name VHDL_FILE fhw_sd/sd_counter_e.vhd -library fhw_sd
39 set_global_assignment -name VHDL_FILE fhw_sd/sd_commands_p.vhd -library fhw_sd
40 set_global_assignment -name VHDL_FILE fhw_sd/sd_globals_p.vhd -library fhw_sd
41 set_global_assignment -name VHDL_FILE fhw_spi/spi_master.vhd -library fhw_spi
42 set_global_assignment -name VHDL_FILE fhw_spi/spi_engine_e.vhd -library fhw_spi
43 set_global_assignment -name VHDL_FILE fhw_spi/spi_shifter_e.vhd -library fhw_spi
44 set_global_assignment -name VHDL_FILE fhw_spi/spi_counter_e.vhd -library fhw_spi
45 set_global_assignment -name VHDL_FILE fhw_spi/spi_starter_e.vhd -library fhw_spi
46 set_global_assignment -name VHDL_FILE fhw_tools/types.vhd -library fhw_tools
47 set_global_assignment -name VHDL_FILE fhw_tools/button.vhd -library fhw_tools
48 set_global_assignment -name VHDL_FILE bos2k9_globals.vhd
49 set_global_assignment -name VHDL_FILE bos2k9_mmu.vhd
50 set_global_assignment -name QIP_FILE mf_block_ram.qip
51 set_global_assignment -name VHDL_FILE bos2k9.vhd
52
53 # Pin & Location Assignments
54 # ==========================
55 set_location_assignment PIN_N2 -to CLOCK_50
56 set_location_assignment PIN_D25 -to GPIO_0[0]
57 set_location_assignment PIN_J22 -to GPIO_0[1]
58 set_location_assignment PIN_E26 -to GPIO_0[2]
59 set_location_assignment PIN_E25 -to GPIO_0[3]
60 set_location_assignment PIN_F24 -to GPIO_0[4]
61 set_location_assignment PIN_F23 -to GPIO_0[5]
62 set_location_assignment PIN_J21 -to GPIO_0[6]
63 set_location_assignment PIN_J20 -to GPIO_0[7]
64 set_location_assignment PIN_F25 -to GPIO_0[8]
65 set_location_assignment PIN_F26 -to GPIO_0[9]
66 set_location_assignment PIN_N18 -to GPIO_0[10]
67 set_location_assignment PIN_P18 -to GPIO_0[11]
68 set_location_assignment PIN_G23 -to GPIO_0[12]
69 set_location_assignment PIN_G24 -to GPIO_0[13]
70 set_location_assignment PIN_K22 -to GPIO_0[14]
71 set_location_assignment PIN_G25 -to GPIO_0[15]
72 set_location_assignment PIN_H23 -to GPIO_0[16]
73 set_location_assignment PIN_H24 -to GPIO_0[17]
74 set_location_assignment PIN_J23 -to GPIO_0[18]
75 set_location_assignment PIN_J24 -to GPIO_0[19]
76 set_location_assignment PIN_H25 -to GPIO_0[20]
77 set_location_assignment PIN_H26 -to GPIO_0[21]
78 set_location_assignment PIN_H19 -to GPIO_0[22]
79 set_location_assignment PIN_K18 -to GPIO_0[23]
80 set_location_assignment PIN_K19 -to GPIO_0[24]
81 set_location_assignment PIN_K21 -to GPIO_0[25]
82 set_location_assignment PIN_K23 -to GPIO_0[26]
83 set_location_assignment PIN_K24 -to GPIO_0[27]
84 set_location_assignment PIN_L21 -to GPIO_0[28]
85 set_location_assignment PIN_L20 -to GPIO_0[29]
86 set_location_assignment PIN_J25 -to GPIO_0[30]
87 set_location_assignment PIN_J26 -to GPIO_0[31]
88 set_location_assignment PIN_L23 -to GPIO_0[32]
89 set_location_assignment PIN_L24 -to GPIO_0[33]
90 set_location_assignment PIN_L25 -to GPIO_0[34]
91 set_location_assignment PIN_L19 -to GPIO_0[35]
92 set_location_assignment PIN_AD24 -to SD_DAT
93 set_location_assignment PIN_AC23 -to SD_DAT3
94 set_location_assignment PIN_Y21 -to SD_CMD
95 set_location_assignment PIN_AD25 -to SD_CLK
96 set_location_assignment PIN_N25 -to SW[0]
97 set_location_assignment PIN_N26 -to SW[1]
98 set_location_assignment PIN_P25 -to SW[2]
99 set_location_assignment PIN_AE14 -to SW[3]
100 set_location_assignment PIN_AF14 -to SW[4]
101 set_location_assignment PIN_AD13 -to SW[5]
102 set_location_assignment PIN_AC13 -to SW[6]
103 set_location_assignment PIN_C13 -to SW[7]
104 set_location_assignment PIN_B13 -to SW[8]
105 set_location_assignment PIN_A13 -to SW[9]
106 set_location_assignment PIN_N1 -to SW[10]
107 set_location_assignment PIN_P1 -to SW[11]
108 set_location_assignment PIN_P2 -to SW[12]
109 set_location_assignment PIN_T7 -to SW[13]
110 set_location_assignment PIN_U3 -to SW[14]
111 set_location_assignment PIN_U4 -to SW[15]
112 set_location_assignment PIN_V1 -to SW[16]
113 set_location_assignment PIN_V2 -to SW[17]
114 set_location_assignment PIN_G26 -to KEY[0]
115 set_location_assignment PIN_N23 -to KEY[1]
116 set_location_assignment PIN_P23 -to KEY[2]
117 set_location_assignment PIN_W26 -to KEY[3]
118 set_location_assignment PIN_AE23 -to LEDR[0]
119 set_location_assignment PIN_AF23 -to LEDR[1]
120 set_location_assignment PIN_AB21 -to LEDR[2]
121 set_location_assignment PIN_AC22 -to LEDR[3]
122 set_location_assignment PIN_AD22 -to LEDR[4]
123 set_location_assignment PIN_AD23 -to LEDR[5]
124 set_location_assignment PIN_AD21 -to LEDR[6]
125 set_location_assignment PIN_AC21 -to LEDR[7]
126 set_location_assignment PIN_AA14 -to LEDR[8]
127 set_location_assignment PIN_Y13 -to LEDR[9]
128 set_location_assignment PIN_AA13 -to LEDR[10]
129 set_location_assignment PIN_AC14 -to LEDR[11]
130 set_location_assignment PIN_AD15 -to LEDR[12]
131 set_location_assignment PIN_AE15 -to LEDR[13]
132 set_location_assignment PIN_AF13 -to LEDR[14]
133 set_location_assignment PIN_AE13 -to LEDR[15]
134 set_location_assignment PIN_AE12 -to LEDR[16]
135 set_location_assignment PIN_AD12 -to LEDR[17]
136 set_location_assignment PIN_AE22 -to LEDG[0]
137 set_location_assignment PIN_AF22 -to LEDG[1]
138 set_location_assignment PIN_W19 -to LEDG[2]
139 set_location_assignment PIN_V18 -to LEDG[3]
140 set_location_assignment PIN_U18 -to LEDG[4]
141 set_location_assignment PIN_U17 -to LEDG[5]
142 set_location_assignment PIN_AA20 -to LEDG[6]
143 set_location_assignment PIN_Y18 -to LEDG[7]
144 set_location_assignment PIN_Y12 -to LEDG[8]
145
146 # Classic Timing Assignments
147 # ==========================
148 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
149 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
150
151 # Analysis & Synthesis Assignments
152 # ================================
153 set_global_assignment -name FAMILY "Cyclone II"
154 set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
155 set_global_assignment -name TOP_LEVEL_ENTITY bos2k9
156
157 # Fitter Assignments
158 # ==================
159 set_global_assignment -name DEVICE EP2C35F672C6
160 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
161 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
162 set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
163
164 # EDA Netlist Writer Assignments
165 # ==============================
166 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
167
168 # Assembler Assignments
169 # =====================
170 set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
171
172 # Simulator Assignments
173 # =====================
174 set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
175
176 # Power Estimation Assignments
177 # ============================
178 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
179 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
180
181 # start EDA_TOOL_SETTINGS(eda_design_synthesis)
182 # ---------------------------------------------
183
184         # Analysis & Synthesis Assignments
185         # ================================
186         set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
187         set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
188         set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
189
190 # end EDA_TOOL_SETTINGS(eda_design_synthesis)
191 # -------------------------------------------
192
193 # start EDA_TOOL_SETTINGS(eda_simulation)
194 # ---------------------------------------
195
196         # EDA Netlist Writer Assignments
197         # ==============================
198         set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
199
200 # end EDA_TOOL_SETTINGS(eda_simulation)
201 # -------------------------------------
202
203 # start EDA_TOOL_SETTINGS(eda_blast_fpga)
204 # ---------------------------------------
205
206         # Analysis & Synthesis Assignments
207         # ================================
208         set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
209
210 # end EDA_TOOL_SETTINGS(eda_blast_fpga)
211 # -------------------------------------
212
213 # start CLOCK(CLOCK_50)
214 # ---------------------
215
216         # Classic Timing Assignments
217         # ==========================
218         set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id CLOCK_50
219
220 # end CLOCK(CLOCK_50)
221 # -------------------
222
223 # start ASSIGNMENT_GROUP(SD)
224 # --------------------------
225
226         # Assignment Group Assignments
227         # ============================
228         set_global_assignment -name ASSIGNMENT_GROUP_MEMBER SD_CLK -section_id SD
229         set_global_assignment -name ASSIGNMENT_GROUP_MEMBER SD_CMD -section_id SD
230         set_global_assignment -name ASSIGNMENT_GROUP_MEMBER SD_DAT -section_id SD
231         set_global_assignment -name ASSIGNMENT_GROUP_MEMBER SD_DAT3 -section_id SD
232
233 # end ASSIGNMENT_GROUP(SD)
234 # ------------------------
235
236 # start IO_STANDARD(3.3-V LVTTL)
237 # ------------------------------
238
239         # Fitter Assignments
240         # ==================
241         set_global_assignment -name OUTPUT_PIN_LOAD 1 -section_id "3.3-V LVTTL"
242
243 # end IO_STANDARD(3.3-V LVTTL)
244 # ----------------------------
245
246 # --------------------
247 # start ENTITY(bos2k9)
248
249         # Classic Timing Assignments
250         # ==========================
251         set_instance_assignment -name CLOCK_SETTINGS CLOCK_50 -to CLOCK_50
252
253         # start LOGICLOCK_REGION(Root Region)
254         # -----------------------------------
255
256                 # LogicLock Region Assignments
257                 # ============================
258                 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
259                 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
260
261         # end LOGICLOCK_REGION(Root Region)
262         # ---------------------------------
263
264         # start DESIGN_PARTITION(Top)
265         # ---------------------------
266
267                 # Incremental Compilation Assignments
268                 # ===================================
269                 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
270                 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
271                 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
272
273         # end DESIGN_PARTITION(Top)
274         # -------------------------
275
276 # end ENTITY(bos2k9)
277 # ------------------