1 -----------------------------------------------------------------------
2 -- Copyright (c) 2009 Malte S. Stretz <http://msquadrat.de>
4 -- The project top level entity.
6 -- It implements a simple test setup which can read data from an SD
7 -- card. Blocks are read in 512 Byte blocks, so both block addresses
8 -- and byte addresses (relative to the block start) can be specified.
9 -- The system starts up doing nothing, an init button has to be pressed
10 -- to initialize the card and afterwards the selected block can be read
11 -- to an internal buffer.
13 -- This is designed around the DE2 evaluation board. To simplify
14 -- development, the ports of the entity are named after the file
15 -- `DE2_Pin_Table.pdf`, which is part of the DE2 documentation.
16 -- The PDF file was converted to a TCL file and is included in this
17 -- project as `de2_pins.tcl` and can be copied to the `bos2k9.qsf`
18 -- project file. This has the side effect that Quartus will complain
19 -- that some of these pins are stuck to GND or not used; these
20 -- warnings can be ignored.
22 -- The following pins are used:
23 -- * `CLOCK_50` is the 50 MHz system clock.
24 -- * `KEY` are the four push button which are low-active.
25 -- * `SW` are the eighteen on-off switches.
26 -- * `LEDR` are the eighteen red LEDs above the switches.
27 -- * `LEDG` are the nine green LEDs; the low eight are located above
28 -- the push buttons, the ninth is above the row of red LEDs.
29 -- * `SD_DAT` is the SPI MISO.
30 -- * `SD_CMD` is the SPI MOSI.
31 -- * `SD_DAT3` is the SPI CS.
32 -- * `SD_CLK` is the SPI SCK.
34 -- LEDG(0) should be always on and represents a powered system. The
35 -- `reset` is wired to `SW(17)`, so the switch should be off when these
36 -- system is started. Once `reset` is off (ie. the switch on), the card
37 -- can be initialized (and later reset) by pressing `KEY(0)`. Once
38 -- LEDG(2) is led, the system is ready to read a block; if an error
39 -- occurs, LEDG(1) is switched on instead.
41 -- The low eight bits of the block address can be specified by the
42 -- first eight `SW`es, ie. SW(0) to SW(7). Only the first 256 blocks
43 -- of 4096 possible ones (on 2 GiB SD cards; SDHC is not supported) can
44 -- be read. `KEY(1)` starts the reading of the selected block.
46 -- The used `button` entity ensures that even with really slow fingers,
47 -- the button press is only signaled once. As the buttons on the DE2
48 -- board tend to break, this cannot be ensured but a longer press
49 -- doesn't break anything.
51 -- The currently via SW(8) to SW(15) selected byte is displayed on the
52 -- LEDs LEDR(0) to LEDR(7).
54 -- Because only eight address bits are wired, only half the block can
55 -- be displayed. Both this and the above limitation doesn't matter as
56 -- this is a test setup only.
58 -- For debugging purposes, the SPI bus is also wired to the LEDs
59 -- LEDG(7) to LEDG(4).
60 -----------------------------------------------------------------------
63 use ieee.std_logic_1164.all;
64 use ieee.numeric_std.all;
71 use fhw_tools.types.all;
73 use work.bos2k9_globals.all;
75 -----------------------------------------------------------------------
79 CLOCK_50 : in std_logic;
81 KEY : in std_logic_vector(3 downto 0);
82 SW : in std_logic_vector(17 downto 0);
83 LEDR : out std_logic_vector(17 downto 0);
84 LEDG : out std_logic_vector(8 downto 0);
86 UART_RXD : in std_logic;
87 UART_TXD : out std_logic;
89 SD_DAT : in std_logic;
90 SD_CMD : out std_logic;
91 SD_DAT3 : out std_logic;
92 SD_CLK : out std_logic);
95 -----------------------------------------------------------------------
97 architecture board of bos2k9 is
101 clock_interval : time := clock_interval_c;
102 clock_divider : positive := sd_clock_div_c);
108 ready : out std_logic;
109 error : out std_logic;
111 address : in std_logic_block_address_t;
112 start : in std_logic;
113 rxd : out std_logic_byte_t;
117 mosi : out std_logic;
122 component bos2k9_counter is
130 done : out std_logic);
133 component bos2k9_pump is
135 clock_divider : positive := ser_clock_div_c;
136 parity_enabled : std_logic := ser_parity_enabled_c;
137 parity_type : std_logic := ser_even_parity_c);
139 clock : in std_logic;
140 reset : in std_logic;
143 txd : in std_logic_byte_t;
153 input : in std_ulogic;
154 output : out std_ulogic);
157 signal clock_s : std_logic;
158 signal reset_s : std_logic;
160 signal ready_led_s : std_logic;
161 signal error_led_s : std_logic;
162 signal busy_led_s : std_logic;
164 signal read_btn_s : std_logic;
166 signal byte_led_s : std_logic_vector(7 downto 0);
167 signal byte_sw1_s : std_logic_vector(7 downto 0);
169 signal spi_s : spi_bus_t;
170 signal ser_s : ser_bus_t;
174 reset_s <= not SW(17);
176 read_button : button port map(clock_s, reset_s,
178 output => read_btn_s);
180 spi_s.miso <= SD_DAT;
181 SD_CMD <= spi_s.mosi;
185 UART_TXD <= ser_s.tx;
186 ser_s.rx <= UART_RXD;
208 byte_sw1_s <= SW(7 downto 0);
212 signal sd_init_s : std_logic;
213 signal sd_ready_s : std_logic;
214 signal sd_error_s : std_logic;
215 signal sd_address_s : std_logic_block_address_t;
216 signal sd_start_s : std_logic;
217 signal sd_data_s : std_logic_byte_t;
218 signal sd_latch_s : std_logic;
219 signal sd_shift_s : std_logic;
221 signal pumping_s : std_logic;
224 -- Map the board outputs.
225 ready_led_s <= sd_ready_s;
226 error_led_s <= sd_error_s;
227 busy_led_s <= pumping_s;
228 byte_led_s <= (others => '0');
230 -- We can address the first 256 blocks only.
231 sd_address_s(std_logic_block_address_t'high downto std_logic_byte_t'high + 1) <= (others => '0');
232 sd_address_s(std_logic_byte_t'range) <= byte_sw1_s;
234 sd_start_s <= read_btn_s and sd_ready_s and not pumping_s;
236 sd_io : sd_host port map(
243 address => sd_address_s,
252 sd_to : bos2k9_counter generic map(
253 cnt => init_ticks_c) port map(
260 pump : bos2k9_pump port map(