1 -----------------------------------------------------------------------
2 -- Copyright (c) 2009 Malte S. Stretz <http://msquadrat.de>
4 -- The project top level entity.
6 -- It implements a simple test setup which can read data from an SD
7 -- card. Blocks are read in 512 Byte blocks, so both block addresses
8 -- and byte addresses (relative to the block start) can be specified.
9 -- The system starts up doing nothing, an init button has to be pressed
10 -- to initialize the card and afterwards the selected block can be read
11 -- to an internal buffer.
13 -- This is designed around the DE2 evaluation board. To simplify
14 -- development, the ports of the entity are named after the file
15 -- `DE2_Pin_Table.pdf`, which is part of the DE2 documentation.
16 -- The PDF file was converted to a TCL file and is included in this
17 -- project as `de2_pins.tcl` and can be copied to the `bos2k9.qsf`
18 -- project file. This has the side effect that Quartus will complain
19 -- that some of these pins are stuck to GND or not used; these
20 -- warnings can be ignored.
22 -- The following pins are used:
23 -- * `CLOCK_50` is the 50 MHz system clock.
24 -- * `KEY` are the four push button which are low-active.
25 -- * `SW` are the eighteen on-off switches.
26 -- * `LEDR` are the eighteen red LEDs above the switches.
27 -- * `LEDG` are the nine green LEDs; the low eight are located above
28 -- the push buttons, the ninth is above the row of red LEDs.
29 -- * `SD_DAT` is the SPI MISO.
30 -- * `SD_CMD` is the SPI MOSI.
31 -- * `SD_DAT3` is the SPI CS.
32 -- * `SD_CLK` is the SPI SCK.
33 -- * `UART_RXD` is the serial input.
34 -- * `UART_TXD` is the serial output.
36 -- LEDG(0) should be always on and represents a powered system. The
37 -- `reset` is wired to `SW(17)`, so the switch should be off when these
38 -- system is started. Once `reset` is off (ie. the switch on), the card
39 -- is initialized as soon as it is inserted. Whe n this is successful,
40 -- LEDG(2) is led, the system is ready to read a block; if an error
41 -- occurs, LEDG(1) is switched on instead.
43 -- The low eight bits of the block address can be specified by the
44 -- first eight `SW`es, ie. SW(0) to SW(7). Only the first 256 blocks
45 -- of 4096 possible ones (on 2 GiB SD cards; SDHC is not supported) can
46 -- be read. `KEY(1)` starts the reading of the selected block.
48 -- The used `button` entity ensures that even with really slow fingers,
49 -- the button press is only signaled once. As the buttons on the DE2
50 -- board tend to break, this cannot be ensured but a longer press
51 -- doesn't break anything.
53 -- The whole block is output via `UART_TXD`.
55 -- For debugging purposes, the SPI bus is also wired to the LEDs
56 -- LEDG(7) to LEDG(4).
57 -----------------------------------------------------------------------
60 use ieee.std_logic_1164.all;
61 use ieee.numeric_std.all;
68 use fhw_tools.types.all;
70 use work.bos2k9_globals.all;
72 -----------------------------------------------------------------------
76 CLOCK_50 : in std_logic;
78 KEY : in std_logic_vector(3 downto 0);
79 SW : in std_logic_vector(17 downto 0);
80 LEDR : out std_logic_vector(17 downto 0);
81 LEDG : out std_logic_vector(8 downto 0);
83 UART_RXD : in std_logic;
84 UART_TXD : out std_logic;
86 SD_DAT : in std_logic;
87 SD_CMD : out std_logic;
88 SD_DAT3 : out std_logic;
89 SD_CLK : out std_logic);
92 -----------------------------------------------------------------------
94 architecture board of bos2k9 is
98 clock_interval : time := clock_interval_c;
99 clock_divider : positive := sd_clock_div_c);
105 ready : out std_logic;
106 error : out std_logic;
108 address : in std_logic_block_address_t;
109 start : in std_logic;
110 rxd : out std_logic_byte_t;
114 mosi : out std_logic;
119 component bos2k9_counter is
127 done : out std_logic);
130 component bos2k9_pump is
132 clock_divider : positive := ser_clock_div_c;
133 parity_enabled : std_logic := ser_parity_enabled_c;
134 parity_type : std_logic := ser_even_parity_c);
136 clock : in std_logic;
137 reset : in std_logic;
140 txd : in std_logic_byte_t;
150 input : in std_ulogic;
151 output : out std_ulogic);
154 signal clock_s : std_logic;
155 signal reset_s : std_logic;
157 signal ready_led_s : std_logic;
158 signal error_led_s : std_logic;
159 signal busy_led_s : std_logic;
161 signal read_btn_s : std_logic;
163 signal byte_led_s : std_logic_vector(7 downto 0);
164 signal byte_sw1_s : std_logic_vector(7 downto 0);
166 signal spi_s : spi_bus_t;
167 signal ser_s : ser_bus_t;
171 reset_s <= not SW(17);
173 read_button : button port map(clock_s, reset_s,
175 output => read_btn_s);
177 spi_s.miso <= SD_DAT;
178 SD_CMD <= spi_s.mosi;
182 UART_TXD <= ser_s.tx;
183 ser_s.rx <= UART_RXD;
205 byte_sw1_s <= SW(7 downto 0);
209 signal sd_init_s : std_logic;
210 signal sd_ready_s : std_logic;
211 signal sd_error_s : std_logic;
212 signal sd_address_s : std_logic_block_address_t;
213 signal sd_start_s : std_logic;
214 signal sd_data_s : std_logic_byte_t;
215 signal sd_latch_s : std_logic;
216 signal sd_shift_s : std_logic;
218 signal pumping_s : std_logic;
221 -- Map the board outputs.
222 ready_led_s <= sd_ready_s;
223 error_led_s <= sd_error_s;
224 busy_led_s <= pumping_s;
225 byte_led_s <= (others => '0');
227 -- We can address the first 256 blocks only.
228 sd_address_s(std_logic_block_address_t'high downto std_logic_byte_t'high + 1) <= (others => '0');
229 sd_address_s(std_logic_byte_t'range) <= byte_sw1_s;
231 -- Make sure we can't accidently start another read action while
232 -- something else is still going on.
233 sd_start_s <= read_btn_s and sd_ready_s and not pumping_s;
235 -- Magic wiring between the `sd_host` and the timeout/poll counter:
236 -- The counter will trigger the `init` port each `init_ticks_c`
237 -- but once the `sd_host` is initialized, the `ready` line will
238 -- keep the counter via the `clr` line at zero.
239 sd_io : sd_host port map(
246 address => sd_address_s,
255 sd_to : bos2k9_counter generic map(
256 cnt => init_ticks_c) port map(
263 pump : bos2k9_pump port map(