One fine day we might create our ModelSim project files on demand.
[bos2k9.git] / mf_block_ram.vhd
1 -- megafunction wizard: %RAM: 2-PORT%
2 -- GENERATION: STANDARD
3 -- VERSION: WM1.0
4 -- MODULE: altsyncram 
5
6 -- ============================================================
7 -- File Name: mf_block_ram.vhd
8 -- Megafunction Name(s):
9 --                      altsyncram
10 --
11 -- Simulation Library Files(s):
12 --                      altera_mf
13 -- ============================================================
14 -- ************************************************************
15 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16 --
17 -- 8.1 Build 163 10/28/2008 SJ Web Edition
18 -- ************************************************************
19
20
21 --Copyright (C) 1991-2008 Altera Corporation
22 --Your use of Altera Corporation's design tools, logic functions 
23 --and other software and tools, and its AMPP partner logic 
24 --functions, and any output files from any of the foregoing 
25 --(including device programming or simulation files), and any 
26 --associated documentation or information are expressly subject 
27 --to the terms and conditions of the Altera Program License 
28 --Subscription Agreement, Altera MegaCore Function License 
29 --Agreement, or other applicable license agreement, including, 
30 --without limitation, that your use is for the sole purpose of 
31 --programming logic devices manufactured by Altera and sold by 
32 --Altera or its authorized distributors.  Please refer to the 
33 --applicable agreement for further details.
34
35
36 LIBRARY ieee;
37 USE ieee.std_logic_1164.all;
38
39 LIBRARY altera_mf;
40 USE altera_mf.all;
41
42 ENTITY mf_block_ram IS
43         PORT
44         (
45                 clock           : IN STD_LOGIC ;
46                 data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
47                 rdaddress               : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
48                 wraddress               : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
49                 wren            : IN STD_LOGIC  := '1';
50                 q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
51         );
52 END mf_block_ram;
53
54
55 ARCHITECTURE SYN OF mf_block_ram IS
56
57         SIGNAL sub_wire0        : STD_LOGIC_VECTOR (7 DOWNTO 0);
58
59
60
61         COMPONENT altsyncram
62         GENERIC (
63                 address_reg_b           : STRING;
64                 clock_enable_input_a            : STRING;
65                 clock_enable_input_b            : STRING;
66                 clock_enable_output_a           : STRING;
67                 clock_enable_output_b           : STRING;
68                 intended_device_family          : STRING;
69                 lpm_type                : STRING;
70                 numwords_a              : NATURAL;
71                 numwords_b              : NATURAL;
72                 operation_mode          : STRING;
73                 outdata_aclr_b          : STRING;
74                 outdata_reg_b           : STRING;
75                 power_up_uninitialized          : STRING;
76                 ram_block_type          : STRING;
77                 read_during_write_mode_mixed_ports              : STRING;
78                 widthad_a               : NATURAL;
79                 widthad_b               : NATURAL;
80                 width_a         : NATURAL;
81                 width_b         : NATURAL;
82                 width_byteena_a         : NATURAL
83         );
84         PORT (
85                         wren_a  : IN STD_LOGIC ;
86                         clock0  : IN STD_LOGIC ;
87                         address_a       : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
88                         address_b       : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
89                         q_b     : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
90                         data_a  : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
91         );
92         END COMPONENT;
93
94 BEGIN
95         q    <= sub_wire0(7 DOWNTO 0);
96
97         altsyncram_component : altsyncram
98         GENERIC MAP (
99                 address_reg_b => "CLOCK0",
100                 clock_enable_input_a => "BYPASS",
101                 clock_enable_input_b => "BYPASS",
102                 clock_enable_output_a => "BYPASS",
103                 clock_enable_output_b => "BYPASS",
104                 intended_device_family => "Cyclone II",
105                 lpm_type => "altsyncram",
106                 numwords_a => 512,
107                 numwords_b => 512,
108                 operation_mode => "DUAL_PORT",
109                 outdata_aclr_b => "NONE",
110                 outdata_reg_b => "CLOCK0",
111                 power_up_uninitialized => "FALSE",
112                 ram_block_type => "M4K",
113                 read_during_write_mode_mixed_ports => "DONT_CARE",
114                 widthad_a => 9,
115                 widthad_b => 9,
116                 width_a => 8,
117                 width_b => 8,
118                 width_byteena_a => 1
119         )
120         PORT MAP (
121                 wren_a => wren,
122                 clock0 => clock,
123                 address_a => wraddress,
124                 address_b => rdaddress,
125                 data_a => data,
126                 q_b => sub_wire0
127         );
128
129
130
131 END SYN;
132
133 -- ============================================================
134 -- CNX file retrieval info
135 -- ============================================================
136 -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
137 -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
138 -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
139 -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
140 -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
141 -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
142 -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
143 -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
144 -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
145 -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
146 -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
147 -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
148 -- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
149 -- Retrieval info: PRIVATE: CLRq NUMERIC "0"
150 -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
151 -- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
152 -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
153 -- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
154 -- Retrieval info: PRIVATE: Clock NUMERIC "0"
155 -- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
156 -- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
157 -- Retrieval info: PRIVATE: ECC NUMERIC "0"
158 -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
159 -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
160 -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
161 -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
162 -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
163 -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
164 -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
165 -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
166 -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
167 -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
168 -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
169 -- Retrieval info: PRIVATE: MIFfilename STRING ""
170 -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
171 -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
172 -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
173 -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
174 -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
175 -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
176 -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
177 -- Retrieval info: PRIVATE: REGdata NUMERIC "1"
178 -- Retrieval info: PRIVATE: REGq NUMERIC "1"
179 -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
180 -- Retrieval info: PRIVATE: REGrren NUMERIC "1"
181 -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
182 -- Retrieval info: PRIVATE: REGwren NUMERIC "1"
183 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
184 -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
185 -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
186 -- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
187 -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
188 -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
189 -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
190 -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
191 -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
192 -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
193 -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
194 -- Retrieval info: PRIVATE: enable NUMERIC "0"
195 -- Retrieval info: PRIVATE: rden NUMERIC "0"
196 -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
197 -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
198 -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
199 -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
200 -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
201 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
202 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
203 -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
204 -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
205 -- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
206 -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
207 -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
208 -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
209 -- Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
210 -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
211 -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
212 -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
213 -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
214 -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
215 -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
216 -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
217 -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
218 -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
219 -- Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL rdaddress[8..0]
220 -- Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL wraddress[8..0]
221 -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
222 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
223 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
224 -- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
225 -- Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
226 -- Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
227 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
228 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
229 -- Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram.vhd TRUE
230 -- Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram.inc FALSE
231 -- Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram.cmp FALSE
232 -- Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram.bsf FALSE
233 -- Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram_inst.vhd FALSE
234 -- Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram_waveforms.html FALSE
235 -- Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram_wave*.jpg FALSE
236 -- Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram_syn.v TRUE
237 -- Retrieval info: LIB_FILE: altera_mf