One fine day we might create our ModelSim project files on demand.
[bos2k9.git] / mf_block_ram_syn.v
1 // megafunction wizard: %RAM: 2-PORT%
2 // GENERATION: STANDARD
3 // VERSION: WM1.0
4 // MODULE: altsyncram 
5
6 // ============================================================
7 // File Name: mf_block_ram.v
8 // Megafunction Name(s):
9 //                      altsyncram
10 //
11 // Simulation Library Files(s):
12 //                      altera_mf
13 // ============================================================
14 // ************************************************************
15 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16 //
17 // 8.1 Build 163 10/28/2008 SJ Web Edition
18 // ************************************************************
19
20
21 //Copyright (C) 1991-2008 Altera Corporation
22 //Your use of Altera Corporation's design tools, logic functions 
23 //and other software and tools, and its AMPP partner logic 
24 //functions, and any output files from any of the foregoing 
25 //(including device programming or simulation files), and any 
26 //associated documentation or information are expressly subject 
27 //to the terms and conditions of the Altera Program License 
28 //Subscription Agreement, Altera MegaCore Function License 
29 //Agreement, or other applicable license agreement, including, 
30 //without limitation, that your use is for the sole purpose of 
31 //programming logic devices manufactured by Altera and sold by 
32 //Altera or its authorized distributors.  Please refer to the 
33 //applicable agreement for further details.
34
35
36 //altsyncram ADDRESS_REG_B="CLOCK0" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" DEVICE_FAMILY="Cyclone II" NUMWORDS_A=512 NUMWORDS_B=512 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="CLOCK0" POWER_UP_UNINITIALIZED="FALSE" RAM_BLOCK_TYPE="M4K" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=9 WIDTHAD_B=9 address_a address_b clock0 data_a q_b wren_a
37 //VERSION_BEGIN 8.1 cbx_altsyncram 2008:08:26:11:57:11:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_stratixiii 2008:07:11:13:32:02:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ  VERSION_END
38 // synthesis VERILOG_INPUT_VERSION VERILOG_2001
39 // altera message_off 10463
40
41
42 //synthesis_resources = M4K 1 
43 //synopsys translate_off
44 `timescale 1 ps / 1 ps
45 //synopsys translate_on
46 (* ALTERA_ATTRIBUTE = {"OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"} *)
47 module  mf_block_ram_altsyncram
48         ( 
49         address_a,
50         address_b,
51         clock0,
52         data_a,
53         q_b,
54         wren_a) /* synthesis synthesis_clearbox=1 */;
55         input   [8:0]  address_a;
56         input   [8:0]  address_b;
57         input   clock0;
58         input   [7:0]  data_a;
59         output   [7:0]  q_b;
60         input   wren_a;
61
62         wire  [0:0]   wire_ram_block1a_0portbdataout;
63         wire  [0:0]   wire_ram_block1a_1portbdataout;
64         wire  [0:0]   wire_ram_block1a_2portbdataout;
65         wire  [0:0]   wire_ram_block1a_3portbdataout;
66         wire  [0:0]   wire_ram_block1a_4portbdataout;
67         wire  [0:0]   wire_ram_block1a_5portbdataout;
68         wire  [0:0]   wire_ram_block1a_6portbdataout;
69         wire  [0:0]   wire_ram_block1a_7portbdataout;
70         wire  [8:0]  address_a_wire;
71         wire  [8:0]  address_b_wire;
72
73         cycloneii_ram_block   ram_block1a_0
74         ( 
75         .clk0(clock0),
76         .portaaddr({address_a_wire[8:0]}),
77         .portadatain({data_a[0]}),
78         .portadataout(),
79         .portawe(wren_a),
80         .portbaddr({address_b_wire[8:0]}),
81         .portbdataout(wire_ram_block1a_0portbdataout[0:0]),
82         .portbrewe(1'b1)
83         `ifdef FORMAL_VERIFICATION
84         `else
85         // synopsys translate_off
86         `endif
87         ,
88         .clk1(1'b0),
89         .clr0(1'b0),
90         .clr1(1'b0),
91         .ena0(1'b1),
92         .ena1(1'b1),
93         .portaaddrstall(1'b0),
94         .portabyteenamasks({1{1'b1}}),
95         .portbaddrstall(1'b0),
96         .portbbyteenamasks({1{1'b1}}),
97         .portbdatain({1{1'b0}})
98         `ifdef FORMAL_VERIFICATION
99         `else
100         // synopsys translate_on
101         `endif
102         // synopsys translate_off
103         ,
104         .devclrn(1'b1),
105         .devpor(1'b1)
106         // synopsys translate_on
107         );
108         defparam
109                 ram_block1a_0.connectivity_checking = "OFF",
110                 ram_block1a_0.logical_ram_name = "ALTSYNCRAM",
111                 ram_block1a_0.mixed_port_feed_through_mode = "dont_care",
112                 ram_block1a_0.operation_mode = "dual_port",
113                 ram_block1a_0.port_a_address_width = 9,
114                 ram_block1a_0.port_a_data_width = 1,
115                 ram_block1a_0.port_a_disable_ce_on_input_registers = "on",
116                 ram_block1a_0.port_a_first_address = 0,
117                 ram_block1a_0.port_a_first_bit_number = 0,
118                 ram_block1a_0.port_a_last_address = 511,
119                 ram_block1a_0.port_a_logical_ram_depth = 512,
120                 ram_block1a_0.port_a_logical_ram_width = 8,
121                 ram_block1a_0.port_b_address_clock = "clock0",
122                 ram_block1a_0.port_b_address_width = 9,
123                 ram_block1a_0.port_b_data_out_clear = "none",
124                 ram_block1a_0.port_b_data_out_clock = "clock0",
125                 ram_block1a_0.port_b_data_width = 1,
126                 ram_block1a_0.port_b_disable_ce_on_input_registers = "on",
127                 ram_block1a_0.port_b_disable_ce_on_output_registers = "on",
128                 ram_block1a_0.port_b_first_address = 0,
129                 ram_block1a_0.port_b_first_bit_number = 0,
130                 ram_block1a_0.port_b_last_address = 511,
131                 ram_block1a_0.port_b_logical_ram_depth = 512,
132                 ram_block1a_0.port_b_logical_ram_width = 8,
133                 ram_block1a_0.port_b_read_enable_write_enable_clock = "clock0",
134                 ram_block1a_0.power_up_uninitialized = "false",
135                 ram_block1a_0.ram_block_type = "M4K",
136                 ram_block1a_0.lpm_type = "cycloneii_ram_block",
137                 ram_block1a_0.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
138         cycloneii_ram_block   ram_block1a_1
139         ( 
140         .clk0(clock0),
141         .portaaddr({address_a_wire[8:0]}),
142         .portadatain({data_a[1]}),
143         .portadataout(),
144         .portawe(wren_a),
145         .portbaddr({address_b_wire[8:0]}),
146         .portbdataout(wire_ram_block1a_1portbdataout[0:0]),
147         .portbrewe(1'b1)
148         `ifdef FORMAL_VERIFICATION
149         `else
150         // synopsys translate_off
151         `endif
152         ,
153         .clk1(1'b0),
154         .clr0(1'b0),
155         .clr1(1'b0),
156         .ena0(1'b1),
157         .ena1(1'b1),
158         .portaaddrstall(1'b0),
159         .portabyteenamasks({1{1'b1}}),
160         .portbaddrstall(1'b0),
161         .portbbyteenamasks({1{1'b1}}),
162         .portbdatain({1{1'b0}})
163         `ifdef FORMAL_VERIFICATION
164         `else
165         // synopsys translate_on
166         `endif
167         // synopsys translate_off
168         ,
169         .devclrn(1'b1),
170         .devpor(1'b1)
171         // synopsys translate_on
172         );
173         defparam
174                 ram_block1a_1.connectivity_checking = "OFF",
175                 ram_block1a_1.logical_ram_name = "ALTSYNCRAM",
176                 ram_block1a_1.mixed_port_feed_through_mode = "dont_care",
177                 ram_block1a_1.operation_mode = "dual_port",
178                 ram_block1a_1.port_a_address_width = 9,
179                 ram_block1a_1.port_a_data_width = 1,
180                 ram_block1a_1.port_a_disable_ce_on_input_registers = "on",
181                 ram_block1a_1.port_a_first_address = 0,
182                 ram_block1a_1.port_a_first_bit_number = 1,
183                 ram_block1a_1.port_a_last_address = 511,
184                 ram_block1a_1.port_a_logical_ram_depth = 512,
185                 ram_block1a_1.port_a_logical_ram_width = 8,
186                 ram_block1a_1.port_b_address_clock = "clock0",
187                 ram_block1a_1.port_b_address_width = 9,
188                 ram_block1a_1.port_b_data_out_clear = "none",
189                 ram_block1a_1.port_b_data_out_clock = "clock0",
190                 ram_block1a_1.port_b_data_width = 1,
191                 ram_block1a_1.port_b_disable_ce_on_input_registers = "on",
192                 ram_block1a_1.port_b_disable_ce_on_output_registers = "on",
193                 ram_block1a_1.port_b_first_address = 0,
194                 ram_block1a_1.port_b_first_bit_number = 1,
195                 ram_block1a_1.port_b_last_address = 511,
196                 ram_block1a_1.port_b_logical_ram_depth = 512,
197                 ram_block1a_1.port_b_logical_ram_width = 8,
198                 ram_block1a_1.port_b_read_enable_write_enable_clock = "clock0",
199                 ram_block1a_1.power_up_uninitialized = "false",
200                 ram_block1a_1.ram_block_type = "M4K",
201                 ram_block1a_1.lpm_type = "cycloneii_ram_block",
202                 ram_block1a_1.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
203         cycloneii_ram_block   ram_block1a_2
204         ( 
205         .clk0(clock0),
206         .portaaddr({address_a_wire[8:0]}),
207         .portadatain({data_a[2]}),
208         .portadataout(),
209         .portawe(wren_a),
210         .portbaddr({address_b_wire[8:0]}),
211         .portbdataout(wire_ram_block1a_2portbdataout[0:0]),
212         .portbrewe(1'b1)
213         `ifdef FORMAL_VERIFICATION
214         `else
215         // synopsys translate_off
216         `endif
217         ,
218         .clk1(1'b0),
219         .clr0(1'b0),
220         .clr1(1'b0),
221         .ena0(1'b1),
222         .ena1(1'b1),
223         .portaaddrstall(1'b0),
224         .portabyteenamasks({1{1'b1}}),
225         .portbaddrstall(1'b0),
226         .portbbyteenamasks({1{1'b1}}),
227         .portbdatain({1{1'b0}})
228         `ifdef FORMAL_VERIFICATION
229         `else
230         // synopsys translate_on
231         `endif
232         // synopsys translate_off
233         ,
234         .devclrn(1'b1),
235         .devpor(1'b1)
236         // synopsys translate_on
237         );
238         defparam
239                 ram_block1a_2.connectivity_checking = "OFF",
240                 ram_block1a_2.logical_ram_name = "ALTSYNCRAM",
241                 ram_block1a_2.mixed_port_feed_through_mode = "dont_care",
242                 ram_block1a_2.operation_mode = "dual_port",
243                 ram_block1a_2.port_a_address_width = 9,
244                 ram_block1a_2.port_a_data_width = 1,
245                 ram_block1a_2.port_a_disable_ce_on_input_registers = "on",
246                 ram_block1a_2.port_a_first_address = 0,
247                 ram_block1a_2.port_a_first_bit_number = 2,
248                 ram_block1a_2.port_a_last_address = 511,
249                 ram_block1a_2.port_a_logical_ram_depth = 512,
250                 ram_block1a_2.port_a_logical_ram_width = 8,
251                 ram_block1a_2.port_b_address_clock = "clock0",
252                 ram_block1a_2.port_b_address_width = 9,
253                 ram_block1a_2.port_b_data_out_clear = "none",
254                 ram_block1a_2.port_b_data_out_clock = "clock0",
255                 ram_block1a_2.port_b_data_width = 1,
256                 ram_block1a_2.port_b_disable_ce_on_input_registers = "on",
257                 ram_block1a_2.port_b_disable_ce_on_output_registers = "on",
258                 ram_block1a_2.port_b_first_address = 0,
259                 ram_block1a_2.port_b_first_bit_number = 2,
260                 ram_block1a_2.port_b_last_address = 511,
261                 ram_block1a_2.port_b_logical_ram_depth = 512,
262                 ram_block1a_2.port_b_logical_ram_width = 8,
263                 ram_block1a_2.port_b_read_enable_write_enable_clock = "clock0",
264                 ram_block1a_2.power_up_uninitialized = "false",
265                 ram_block1a_2.ram_block_type = "M4K",
266                 ram_block1a_2.lpm_type = "cycloneii_ram_block",
267                 ram_block1a_2.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
268         cycloneii_ram_block   ram_block1a_3
269         ( 
270         .clk0(clock0),
271         .portaaddr({address_a_wire[8:0]}),
272         .portadatain({data_a[3]}),
273         .portadataout(),
274         .portawe(wren_a),
275         .portbaddr({address_b_wire[8:0]}),
276         .portbdataout(wire_ram_block1a_3portbdataout[0:0]),
277         .portbrewe(1'b1)
278         `ifdef FORMAL_VERIFICATION
279         `else
280         // synopsys translate_off
281         `endif
282         ,
283         .clk1(1'b0),
284         .clr0(1'b0),
285         .clr1(1'b0),
286         .ena0(1'b1),
287         .ena1(1'b1),
288         .portaaddrstall(1'b0),
289         .portabyteenamasks({1{1'b1}}),
290         .portbaddrstall(1'b0),
291         .portbbyteenamasks({1{1'b1}}),
292         .portbdatain({1{1'b0}})
293         `ifdef FORMAL_VERIFICATION
294         `else
295         // synopsys translate_on
296         `endif
297         // synopsys translate_off
298         ,
299         .devclrn(1'b1),
300         .devpor(1'b1)
301         // synopsys translate_on
302         );
303         defparam
304                 ram_block1a_3.connectivity_checking = "OFF",
305                 ram_block1a_3.logical_ram_name = "ALTSYNCRAM",
306                 ram_block1a_3.mixed_port_feed_through_mode = "dont_care",
307                 ram_block1a_3.operation_mode = "dual_port",
308                 ram_block1a_3.port_a_address_width = 9,
309                 ram_block1a_3.port_a_data_width = 1,
310                 ram_block1a_3.port_a_disable_ce_on_input_registers = "on",
311                 ram_block1a_3.port_a_first_address = 0,
312                 ram_block1a_3.port_a_first_bit_number = 3,
313                 ram_block1a_3.port_a_last_address = 511,
314                 ram_block1a_3.port_a_logical_ram_depth = 512,
315                 ram_block1a_3.port_a_logical_ram_width = 8,
316                 ram_block1a_3.port_b_address_clock = "clock0",
317                 ram_block1a_3.port_b_address_width = 9,
318                 ram_block1a_3.port_b_data_out_clear = "none",
319                 ram_block1a_3.port_b_data_out_clock = "clock0",
320                 ram_block1a_3.port_b_data_width = 1,
321                 ram_block1a_3.port_b_disable_ce_on_input_registers = "on",
322                 ram_block1a_3.port_b_disable_ce_on_output_registers = "on",
323                 ram_block1a_3.port_b_first_address = 0,
324                 ram_block1a_3.port_b_first_bit_number = 3,
325                 ram_block1a_3.port_b_last_address = 511,
326                 ram_block1a_3.port_b_logical_ram_depth = 512,
327                 ram_block1a_3.port_b_logical_ram_width = 8,
328                 ram_block1a_3.port_b_read_enable_write_enable_clock = "clock0",
329                 ram_block1a_3.power_up_uninitialized = "false",
330                 ram_block1a_3.ram_block_type = "M4K",
331                 ram_block1a_3.lpm_type = "cycloneii_ram_block",
332                 ram_block1a_3.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
333         cycloneii_ram_block   ram_block1a_4
334         ( 
335         .clk0(clock0),
336         .portaaddr({address_a_wire[8:0]}),
337         .portadatain({data_a[4]}),
338         .portadataout(),
339         .portawe(wren_a),
340         .portbaddr({address_b_wire[8:0]}),
341         .portbdataout(wire_ram_block1a_4portbdataout[0:0]),
342         .portbrewe(1'b1)
343         `ifdef FORMAL_VERIFICATION
344         `else
345         // synopsys translate_off
346         `endif
347         ,
348         .clk1(1'b0),
349         .clr0(1'b0),
350         .clr1(1'b0),
351         .ena0(1'b1),
352         .ena1(1'b1),
353         .portaaddrstall(1'b0),
354         .portabyteenamasks({1{1'b1}}),
355         .portbaddrstall(1'b0),
356         .portbbyteenamasks({1{1'b1}}),
357         .portbdatain({1{1'b0}})
358         `ifdef FORMAL_VERIFICATION
359         `else
360         // synopsys translate_on
361         `endif
362         // synopsys translate_off
363         ,
364         .devclrn(1'b1),
365         .devpor(1'b1)
366         // synopsys translate_on
367         );
368         defparam
369                 ram_block1a_4.connectivity_checking = "OFF",
370                 ram_block1a_4.logical_ram_name = "ALTSYNCRAM",
371                 ram_block1a_4.mixed_port_feed_through_mode = "dont_care",
372                 ram_block1a_4.operation_mode = "dual_port",
373                 ram_block1a_4.port_a_address_width = 9,
374                 ram_block1a_4.port_a_data_width = 1,
375                 ram_block1a_4.port_a_disable_ce_on_input_registers = "on",
376                 ram_block1a_4.port_a_first_address = 0,
377                 ram_block1a_4.port_a_first_bit_number = 4,
378                 ram_block1a_4.port_a_last_address = 511,
379                 ram_block1a_4.port_a_logical_ram_depth = 512,
380                 ram_block1a_4.port_a_logical_ram_width = 8,
381                 ram_block1a_4.port_b_address_clock = "clock0",
382                 ram_block1a_4.port_b_address_width = 9,
383                 ram_block1a_4.port_b_data_out_clear = "none",
384                 ram_block1a_4.port_b_data_out_clock = "clock0",
385                 ram_block1a_4.port_b_data_width = 1,
386                 ram_block1a_4.port_b_disable_ce_on_input_registers = "on",
387                 ram_block1a_4.port_b_disable_ce_on_output_registers = "on",
388                 ram_block1a_4.port_b_first_address = 0,
389                 ram_block1a_4.port_b_first_bit_number = 4,
390                 ram_block1a_4.port_b_last_address = 511,
391                 ram_block1a_4.port_b_logical_ram_depth = 512,
392                 ram_block1a_4.port_b_logical_ram_width = 8,
393                 ram_block1a_4.port_b_read_enable_write_enable_clock = "clock0",
394                 ram_block1a_4.power_up_uninitialized = "false",
395                 ram_block1a_4.ram_block_type = "M4K",
396                 ram_block1a_4.lpm_type = "cycloneii_ram_block",
397                 ram_block1a_4.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
398         cycloneii_ram_block   ram_block1a_5
399         ( 
400         .clk0(clock0),
401         .portaaddr({address_a_wire[8:0]}),
402         .portadatain({data_a[5]}),
403         .portadataout(),
404         .portawe(wren_a),
405         .portbaddr({address_b_wire[8:0]}),
406         .portbdataout(wire_ram_block1a_5portbdataout[0:0]),
407         .portbrewe(1'b1)
408         `ifdef FORMAL_VERIFICATION
409         `else
410         // synopsys translate_off
411         `endif
412         ,
413         .clk1(1'b0),
414         .clr0(1'b0),
415         .clr1(1'b0),
416         .ena0(1'b1),
417         .ena1(1'b1),
418         .portaaddrstall(1'b0),
419         .portabyteenamasks({1{1'b1}}),
420         .portbaddrstall(1'b0),
421         .portbbyteenamasks({1{1'b1}}),
422         .portbdatain({1{1'b0}})
423         `ifdef FORMAL_VERIFICATION
424         `else
425         // synopsys translate_on
426         `endif
427         // synopsys translate_off
428         ,
429         .devclrn(1'b1),
430         .devpor(1'b1)
431         // synopsys translate_on
432         );
433         defparam
434                 ram_block1a_5.connectivity_checking = "OFF",
435                 ram_block1a_5.logical_ram_name = "ALTSYNCRAM",
436                 ram_block1a_5.mixed_port_feed_through_mode = "dont_care",
437                 ram_block1a_5.operation_mode = "dual_port",
438                 ram_block1a_5.port_a_address_width = 9,
439                 ram_block1a_5.port_a_data_width = 1,
440                 ram_block1a_5.port_a_disable_ce_on_input_registers = "on",
441                 ram_block1a_5.port_a_first_address = 0,
442                 ram_block1a_5.port_a_first_bit_number = 5,
443                 ram_block1a_5.port_a_last_address = 511,
444                 ram_block1a_5.port_a_logical_ram_depth = 512,
445                 ram_block1a_5.port_a_logical_ram_width = 8,
446                 ram_block1a_5.port_b_address_clock = "clock0",
447                 ram_block1a_5.port_b_address_width = 9,
448                 ram_block1a_5.port_b_data_out_clear = "none",
449                 ram_block1a_5.port_b_data_out_clock = "clock0",
450                 ram_block1a_5.port_b_data_width = 1,
451                 ram_block1a_5.port_b_disable_ce_on_input_registers = "on",
452                 ram_block1a_5.port_b_disable_ce_on_output_registers = "on",
453                 ram_block1a_5.port_b_first_address = 0,
454                 ram_block1a_5.port_b_first_bit_number = 5,
455                 ram_block1a_5.port_b_last_address = 511,
456                 ram_block1a_5.port_b_logical_ram_depth = 512,
457                 ram_block1a_5.port_b_logical_ram_width = 8,
458                 ram_block1a_5.port_b_read_enable_write_enable_clock = "clock0",
459                 ram_block1a_5.power_up_uninitialized = "false",
460                 ram_block1a_5.ram_block_type = "M4K",
461                 ram_block1a_5.lpm_type = "cycloneii_ram_block",
462                 ram_block1a_5.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
463         cycloneii_ram_block   ram_block1a_6
464         ( 
465         .clk0(clock0),
466         .portaaddr({address_a_wire[8:0]}),
467         .portadatain({data_a[6]}),
468         .portadataout(),
469         .portawe(wren_a),
470         .portbaddr({address_b_wire[8:0]}),
471         .portbdataout(wire_ram_block1a_6portbdataout[0:0]),
472         .portbrewe(1'b1)
473         `ifdef FORMAL_VERIFICATION
474         `else
475         // synopsys translate_off
476         `endif
477         ,
478         .clk1(1'b0),
479         .clr0(1'b0),
480         .clr1(1'b0),
481         .ena0(1'b1),
482         .ena1(1'b1),
483         .portaaddrstall(1'b0),
484         .portabyteenamasks({1{1'b1}}),
485         .portbaddrstall(1'b0),
486         .portbbyteenamasks({1{1'b1}}),
487         .portbdatain({1{1'b0}})
488         `ifdef FORMAL_VERIFICATION
489         `else
490         // synopsys translate_on
491         `endif
492         // synopsys translate_off
493         ,
494         .devclrn(1'b1),
495         .devpor(1'b1)
496         // synopsys translate_on
497         );
498         defparam
499                 ram_block1a_6.connectivity_checking = "OFF",
500                 ram_block1a_6.logical_ram_name = "ALTSYNCRAM",
501                 ram_block1a_6.mixed_port_feed_through_mode = "dont_care",
502                 ram_block1a_6.operation_mode = "dual_port",
503                 ram_block1a_6.port_a_address_width = 9,
504                 ram_block1a_6.port_a_data_width = 1,
505                 ram_block1a_6.port_a_disable_ce_on_input_registers = "on",
506                 ram_block1a_6.port_a_first_address = 0,
507                 ram_block1a_6.port_a_first_bit_number = 6,
508                 ram_block1a_6.port_a_last_address = 511,
509                 ram_block1a_6.port_a_logical_ram_depth = 512,
510                 ram_block1a_6.port_a_logical_ram_width = 8,
511                 ram_block1a_6.port_b_address_clock = "clock0",
512                 ram_block1a_6.port_b_address_width = 9,
513                 ram_block1a_6.port_b_data_out_clear = "none",
514                 ram_block1a_6.port_b_data_out_clock = "clock0",
515                 ram_block1a_6.port_b_data_width = 1,
516                 ram_block1a_6.port_b_disable_ce_on_input_registers = "on",
517                 ram_block1a_6.port_b_disable_ce_on_output_registers = "on",
518                 ram_block1a_6.port_b_first_address = 0,
519                 ram_block1a_6.port_b_first_bit_number = 6,
520                 ram_block1a_6.port_b_last_address = 511,
521                 ram_block1a_6.port_b_logical_ram_depth = 512,
522                 ram_block1a_6.port_b_logical_ram_width = 8,
523                 ram_block1a_6.port_b_read_enable_write_enable_clock = "clock0",
524                 ram_block1a_6.power_up_uninitialized = "false",
525                 ram_block1a_6.ram_block_type = "M4K",
526                 ram_block1a_6.lpm_type = "cycloneii_ram_block",
527                 ram_block1a_6.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
528         cycloneii_ram_block   ram_block1a_7
529         ( 
530         .clk0(clock0),
531         .portaaddr({address_a_wire[8:0]}),
532         .portadatain({data_a[7]}),
533         .portadataout(),
534         .portawe(wren_a),
535         .portbaddr({address_b_wire[8:0]}),
536         .portbdataout(wire_ram_block1a_7portbdataout[0:0]),
537         .portbrewe(1'b1)
538         `ifdef FORMAL_VERIFICATION
539         `else
540         // synopsys translate_off
541         `endif
542         ,
543         .clk1(1'b0),
544         .clr0(1'b0),
545         .clr1(1'b0),
546         .ena0(1'b1),
547         .ena1(1'b1),
548         .portaaddrstall(1'b0),
549         .portabyteenamasks({1{1'b1}}),
550         .portbaddrstall(1'b0),
551         .portbbyteenamasks({1{1'b1}}),
552         .portbdatain({1{1'b0}})
553         `ifdef FORMAL_VERIFICATION
554         `else
555         // synopsys translate_on
556         `endif
557         // synopsys translate_off
558         ,
559         .devclrn(1'b1),
560         .devpor(1'b1)
561         // synopsys translate_on
562         );
563         defparam
564                 ram_block1a_7.connectivity_checking = "OFF",
565                 ram_block1a_7.logical_ram_name = "ALTSYNCRAM",
566                 ram_block1a_7.mixed_port_feed_through_mode = "dont_care",
567                 ram_block1a_7.operation_mode = "dual_port",
568                 ram_block1a_7.port_a_address_width = 9,
569                 ram_block1a_7.port_a_data_width = 1,
570                 ram_block1a_7.port_a_disable_ce_on_input_registers = "on",
571                 ram_block1a_7.port_a_first_address = 0,
572                 ram_block1a_7.port_a_first_bit_number = 7,
573                 ram_block1a_7.port_a_last_address = 511,
574                 ram_block1a_7.port_a_logical_ram_depth = 512,
575                 ram_block1a_7.port_a_logical_ram_width = 8,
576                 ram_block1a_7.port_b_address_clock = "clock0",
577                 ram_block1a_7.port_b_address_width = 9,
578                 ram_block1a_7.port_b_data_out_clear = "none",
579                 ram_block1a_7.port_b_data_out_clock = "clock0",
580                 ram_block1a_7.port_b_data_width = 1,
581                 ram_block1a_7.port_b_disable_ce_on_input_registers = "on",
582                 ram_block1a_7.port_b_disable_ce_on_output_registers = "on",
583                 ram_block1a_7.port_b_first_address = 0,
584                 ram_block1a_7.port_b_first_bit_number = 7,
585                 ram_block1a_7.port_b_last_address = 511,
586                 ram_block1a_7.port_b_logical_ram_depth = 512,
587                 ram_block1a_7.port_b_logical_ram_width = 8,
588                 ram_block1a_7.port_b_read_enable_write_enable_clock = "clock0",
589                 ram_block1a_7.power_up_uninitialized = "false",
590                 ram_block1a_7.ram_block_type = "M4K",
591                 ram_block1a_7.lpm_type = "cycloneii_ram_block",
592                 ram_block1a_7.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
593         assign
594                 address_a_wire = address_a,
595                 address_b_wire = address_b,
596                 q_b = {wire_ram_block1a_7portbdataout[0], wire_ram_block1a_6portbdataout[0], wire_ram_block1a_5portbdataout[0], wire_ram_block1a_4portbdataout[0], wire_ram_block1a_3portbdataout[0], wire_ram_block1a_2portbdataout[0], wire_ram_block1a_1portbdataout[0], wire_ram_block1a_0portbdataout[0]};
597 endmodule //mf_block_ram_altsyncram
598 //VALID FILE
599
600
601 // synopsys translate_off
602 `timescale 1 ps / 1 ps
603 // synopsys translate_on
604 module mf_block_ram (
605         clock,
606         data,
607         rdaddress,
608         wraddress,
609         wren,
610         q)/* synthesis synthesis_clearbox = 1 */;
611
612         input     clock;
613         input   [7:0]  data;
614         input   [8:0]  rdaddress;
615         input   [8:0]  wraddress;
616         input     wren;
617         output  [7:0]  q;
618
619         wire [7:0] sub_wire0;
620         wire [7:0] q = sub_wire0[7:0];
621
622         mf_block_ram_altsyncram mf_block_ram_altsyncram_component (
623                                 .wren_a (wren),
624                                 .clock0 (clock),
625                                 .address_a (wraddress),
626                                 .address_b (rdaddress),
627                                 .data_a (data),
628                                 .q_b (sub_wire0));
629
630 endmodule
631
632 // ============================================================
633 // CNX file retrieval info
634 // ============================================================
635 // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
636 // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
637 // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
638 // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
639 // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
640 // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
641 // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
642 // Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
643 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
644 // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
645 // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
646 // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
647 // Retrieval info: PRIVATE: CLRdata NUMERIC "0"
648 // Retrieval info: PRIVATE: CLRq NUMERIC "0"
649 // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
650 // Retrieval info: PRIVATE: CLRrren NUMERIC "0"
651 // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
652 // Retrieval info: PRIVATE: CLRwren NUMERIC "0"
653 // Retrieval info: PRIVATE: Clock NUMERIC "0"
654 // Retrieval info: PRIVATE: Clock_A NUMERIC "0"
655 // Retrieval info: PRIVATE: Clock_B NUMERIC "0"
656 // Retrieval info: PRIVATE: ECC NUMERIC "0"
657 // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
658 // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
659 // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
660 // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
661 // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
662 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
663 // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
664 // Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
665 // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
666 // Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
667 // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
668 // Retrieval info: PRIVATE: MIFfilename STRING ""
669 // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
670 // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
671 // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
672 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
673 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
674 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
675 // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
676 // Retrieval info: PRIVATE: REGdata NUMERIC "1"
677 // Retrieval info: PRIVATE: REGq NUMERIC "1"
678 // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
679 // Retrieval info: PRIVATE: REGrren NUMERIC "1"
680 // Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
681 // Retrieval info: PRIVATE: REGwren NUMERIC "1"
682 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
683 // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
684 // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
685 // Retrieval info: PRIVATE: VarWidth NUMERIC "0"
686 // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
687 // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
688 // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
689 // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
690 // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
691 // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
692 // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
693 // Retrieval info: PRIVATE: enable NUMERIC "0"
694 // Retrieval info: PRIVATE: rden NUMERIC "0"
695 // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
696 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
697 // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
698 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
699 // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
700 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
701 // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
702 // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
703 // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
704 // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
705 // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
706 // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
707 // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
708 // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
709 // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
710 // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
711 // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
712 // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
713 // Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
714 // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
715 // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
716 // Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
717 // Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
718 // Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL rdaddress[8..0]
719 // Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL wraddress[8..0]
720 // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
721 // Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
722 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
723 // Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
724 // Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
725 // Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
726 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
727 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
728 // Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram.vhd TRUE
729 // Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram.inc FALSE
730 // Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram.cmp FALSE
731 // Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram.bsf FALSE
732 // Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram_inst.vhd FALSE
733 // Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram_waveforms.html FALSE
734 // Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram_wave*.jpg FALSE
735 // Retrieval info: GEN_FILE: TYPE_NORMAL mf_block_ram_syn.v TRUE
736 // Retrieval info: LIB_FILE: altera_mf