1 -----------------------------------------------------------------------
2 -- Copyright (c) 2009 Malte S. Stretz <http://msquadrat.de>
4 -- Testing the top level entity.
5 -----------------------------------------------------------------------
7 use work.bos2k9_globals.all;
10 use fhw_tools.types.all;
13 use ieee.std_logic_1164.all;
14 use ieee.numeric_std.all;
17 use work.txt_util.all;
19 -----------------------------------------------------------------------
23 clock_interval : time := clock_interval_c;
24 spi_filename : string := "bos2k9_t.dat");
27 -----------------------------------------------------------------------
29 architecture test of bos2k9_t is
33 CLOCK_50 : in std_logic;
35 KEY : in std_logic_vector(3 downto 0);
36 SW : in std_logic_vector(17 downto 0);
37 LEDR : out std_logic_vector(17 downto 0);
38 LEDG : out std_logic_vector(8 downto 0);
40 SD_DAT : in std_logic;
41 SD_DAT3 : out std_logic;
42 SD_CMD : out std_logic;
43 SD_CLK : out std_logic);
46 file spi_file : text open read_mode is spi_filename;
47 signal test_s : integer;
49 signal clock_s : std_logic;
50 signal reset_s : std_logic;
52 signal KEY_i_s : std_logic_vector(3 downto 0);
53 signal SW_i_s : std_logic_vector(17 downto 0);
54 signal LEDR_o_s : std_logic_vector(17 downto 0);
55 signal LEDG_o_s : std_logic_vector(8 downto 0);
56 signal SD_DAT_i_s : std_logic;
57 signal SD_DAT3_o_s : std_logic;
58 signal SD_CMD_o_s : std_logic;
59 signal SD_CLK_o_s : std_logic;
61 signal init_s : std_logic;
62 signal ready_s : std_logic;
63 signal start_s : std_logic;
64 signal error_s : std_logic;
65 signal txd_s : std_logic_byte_t;
66 signal rxd_s : std_logic_byte_t;
67 signal spi_s : spi_bus_t;
69 signal addr_sw_s : std_logic_byte_t;
70 signal byte_sw_s : std_logic_byte_t;
71 signal byte_dw_s : std_logic_byte_t;
73 dut : bos2k9 port map(clock_s,
82 SD_DAT_i_s <= spi_s.miso;
83 spi_s.mosi <= SD_CMD_o_s;
84 spi_s.sck <= SD_CLK_o_s;
85 spi_s.cs <= SD_DAT3_o_s;
87 byte_dw_s <= LEDR_o_s(7 downto 0);
88 SW_i_s(7 downto 0) <= addr_sw_s;
89 SW_i_s(15 downto 8) <= byte_sw_s;
91 SW_i_s(17) <= not reset_s;
92 KEY_i_s(0) <= not init_s;
93 KEY_i_s(1) <= not start_s;
94 KEY_i_s(3 downto 2) <= (others => '1');
96 error_s <= LEDG_o_s(0);
97 ready_s <= LEDG_o_s(1);
99 addr_sw_s <= (others => '0');
100 byte_sw_s <= (others => '0');
106 wait until falling_edge(reset_s);
109 wait until rising_edge(clock_s);
112 wait until rising_edge(ready_s);
114 wait until rising_edge(clock_s);
121 procedure read_skip_header is
122 variable line_v : line;
124 readline(spi_file, line_v);
125 end read_skip_header;
126 procedure read_txd_and_rxd is
127 variable line_v : line;
128 variable input_v : string(1 to 17);
129 variable byte_v : std_logic_byte_t;
131 readline(spi_file, line_v);
132 read(line_v, input_v);
134 txd_s <= to_std_logic_vector(input_v(1 to 8));
135 rxd_s <= to_std_logic_vector(input_v(10 to 17));
136 wait until rising_edge(clock_s);
137 end read_txd_and_rxd;
138 variable index_v : integer;
139 variable txd_v : std_logic_byte_t;
142 rxd_s <= (others => 'Z');
143 txd_v := (others => 'U');
146 wait until falling_edge(clock_s);
149 test_s <= test_s + 1;
153 -- Latch on odd edges, shift on even
154 spi_s.miso <= rxd_s(index_v);
155 wait until rising_edge(spi_s.sck);
156 txd_v(0) := spi_s.mosi;
157 wait until falling_edge(spi_s.sck);
158 index_v := index_v - 1;
162 txd_v := txd_v(6 downto 0) & 'U';
164 test_s <= test_s + 1;
165 assert txd_v = txd_s report "unexpected spi data. got: " & str(txd_v) & " expected: " & str(txd_s);
172 -- wait until falling_edge(reset_s);
173 -- test_s <= test_s + 1;
175 -- if (init_s or start_s) = '1' then
176 -- test_s <= test_s + 1;
178 -- wait until rising_edge(clock_s);
185 wait until rising_edge(clock_s);
186 wait until rising_edge(clock_s);
194 wait for clock_interval / 2;
196 wait for clock_interval / 2;