Handle the reset state in the driver, not the parser, triggered by another button.
authorMalte S. Stretz <mss@apache.org>
Wed, 1 Jul 2009 13:52:18 +0000 (15:52 +0200)
committerMalte S. Stretz <mss@apache.org>
Wed, 1 Jul 2009 13:52:18 +0000 (15:52 +0200)
bos2k9.vhd
bos2k9_t.dat
bos2k9_t.vhd
doc/2_sd/sd_flow_e.fsm
fhw_sd/sd_commands_p.vhd
fhw_sd/sd_flow_e.vhd
fhw_sd/sd_host.vhd
fhw_sd/sd_parser_e.vhd
fhw_sd_t/sd_flow_t.vhd
fhw_sd_t/sd_parser_t.vhd

index 0a8d0e6..761ffe4 100644 (file)
@@ -41,8 +41,8 @@ architecture board of bos2k9 is
       clk : in  std_logic;
       rst : in  std_logic;
 
+      init  : in  std_logic;
       ready : out std_logic;
-      busy  : out std_logic;
       error : out std_logic;
       
       address : in  std_logic_block_address_t;
@@ -78,10 +78,10 @@ architecture board of bos2k9 is
   signal clock_s : std_logic;
   signal reset_s : std_logic;
   
-  signal busy_led_s  : std_logic;
   signal ready_led_s : std_logic;
   signal error_led_s : std_logic;
   
+  signal init_btn_s  : std_logic;
   signal start_btn_s : std_logic;
   
   signal byte_led_s  : std_logic_vector(7 downto 0);
@@ -97,8 +97,11 @@ begin
 
   --GPIO_0 <= (others => 'Z');
   
-  start_button : button port map(
+  init_button : button port map(
     input  => KEY(0),
+    output => init_btn_s);
+  start_button : button port map(
+    input  => KEY(1),
     output => start_btn_s);
   
   spi_s.miso <= SD_DAT;
@@ -111,7 +114,6 @@ begin
     6 => spi_s.mosi,
     5 => spi_s.sck,
     4 => spi_s.cs,
-    2 => busy_led_s,
     1 => ready_led_s,
     0 => error_led_s,
     others => '0');
@@ -130,8 +132,8 @@ begin
   byte_sw2_s <= SW(15 downto 8);
   
   guts : block
+    signal sd_init_s    : std_logic;
     signal sd_ready_s   : std_logic;
-    signal sd_busy_s    : std_logic;
     signal sd_error_s   : std_logic;
     signal sd_address_s : std_logic_block_address_t;
     signal sd_start_s   : std_logic;
@@ -142,10 +144,10 @@ begin
     signal bl_address_s : std_logic_byte_address_t;
   begin
 
-    busy_led_s  <= sd_busy_s;
     ready_led_s <= sd_ready_s;
     error_led_s <= sd_error_s;
     
+    sd_init_s  <= init_btn_s;
     sd_start_s <= start_btn_s;
   
     sd_address_s(std_logic_block_address_t'high downto std_logic_byte_t'high + 1) <= (others => '0');
@@ -157,8 +159,8 @@ begin
       clk => clock_s,
       rst => reset_s,
     
+      init    => sd_init_s, 
       ready   => sd_ready_s,
-      busy    => sd_busy_s,
       error   => sd_error_s,
       address => sd_address_s,
       start   => sd_start_s,
index f872f99..fbb8e90 100644 (file)
@@ -1,3 +1,4 @@
+expected response
 11111111 11111111
 11111111 11111111
 11111111 11111111
index 0c6cadd..8c96596 100644 (file)
@@ -58,7 +58,10 @@ architecture test of bos2k9_t is
   signal SD_CMD_o_s   : std_logic;
   signal SD_CLK_o_s   : std_logic;
   
+  signal init_s  : std_logic;
+  signal ready_s : std_logic;
   signal start_s : std_logic;
+  signal error_s : std_logic;
   signal txd_s   : std_logic_byte_t;
   signal rxd_s   : std_logic_byte_t;
   signal spi_s   : spi_bus_t;
@@ -86,21 +89,40 @@ begin
   SW_i_s(15 downto 8) <= byte_sw_s;
   SW_i_s(16)          <= '0';
   SW_i_s(17)          <= not reset_s;
-  KEY_i_s(0)          <= not start_s;
-  KEY_i_s(3 downto 1) <= (others => '1');
+  KEY_i_s(0)          <= not init_s;
+  KEY_i_s(1)          <= not start_s;
+  KEY_i_s(3 downto 2) <= (others => '1');
+  
+  error_s <= LEDG_o_s(0);
+  ready_s <= LEDG_o_s(1);
   
   addr_sw_s <= (others => '0');
   byte_sw_s <= (others => '0');
   
   stimulus : process
   begin
+    init_s  <= '0';
+    start_s <= '0';
+    wait until falling_edge(reset_s);
+    
+    init_s <= '1';
+    wait until rising_edge(clock_s);
+    init_s <= '0';
+    
+    wait until rising_edge(ready_s);
+    start_s <= '1';
+    wait until rising_edge(clock_s);
     start_s <= '0';
-  
     
     wait;
   end process;
   
   slave : process
+    procedure read_skip_header is
+      variable line_v  : line;
+    begin
+      readline(spi_file, line_v);
+    end read_skip_header;
     procedure read_txd_and_rxd is
       variable line_v  : line;
       variable input_v : string(1 to 17);
@@ -115,6 +137,10 @@ begin
     variable index_v : integer;
     variable txd_v   : std_logic_byte_t;
   begin
+    if reset_s = '1' then
+      read_skip_header;
+    end if;
+  
     rxd_s <= (others => 'Z');
     txd_v := (others => 'U');
     test_s <= 0;
@@ -137,10 +163,24 @@ begin
         end if;
         txd_v    := txd_v(6 downto 0) & 'U';
       end loop;
+      test_s <= test_s + 1;
       assert txd_v = txd_s report "unexpected spi data. got: " & str(txd_v) & " expected: " & str(txd_s);
     end loop;
   end process;
   
+  -- mark: process
+  -- begin
+    -- test_s <= -1;
+    -- wait until falling_edge(reset_s);
+    -- test_s <= test_s + 1;
+    -- while true loop
+      -- if (init_s or start_s) = '1' then
+        -- test_s <= test_s + 1;
+      -- end if;
+      -- wait until rising_edge(clock_s);
+    -- end loop;
+  -- end process;
+  
   reset : process
   begin
     reset_s <= '1';
index 2e22fc3..26924e4 100644 (file)
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     <inputnames>i_0</inputnames>
     <outputnames></outputnames>
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+      <to>14</to>
       <inputs default="0" any="0" invert="0" >prev_state</inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="730.1080366349656" c2y="290.6544314438768" c1y="331.3937782336894" description="" straight="0" type="2" ypos="309.066562511751" endx="996.2115650656308" xpos="519.3708482797554" endy="219.9816471658153" c2x="1019.474376710421" >
+    <transition c1x="321.9985479396898" c2y="280.7606834533405" c1y="272.9156729980811" description="" straight="0" type="2" ypos="292.3390192647004" endx="238.1023533249106" xpos="366.7836642873164" endy="206.9447131733004" c2x="235.158618488642" >
       <from>3</from>
-      <to>10</to>
+      <to>9</to>
       <inputs default="0" any="0" invert="0" >prev_state</inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="666.3384989237866" c2y="277.6756487523055" c1y="305.4128833763946" description="" straight="0" type="2" ypos="299.1501180004836" endx="893.218800784901" xpos="519.8983479932294" endy="218.9384141282165" c2x="915.7786498543438" >
+    <transition c1x="254.416307425354" c2y="334.2756517040952" c1y="354.7121748626623" description="" straight="0" type="2" ypos="324.8885438199983" endx="100.7317658498867" xpos="368.2229123600034" endy="222.758589264898" c2x="204.3525229018055" >
       <from>3</from>
-      <to>14</to>
-      <inputs default="0" any="0" invert="0" >prev_state</inputs>
+      <to>0</to>
+      <inputs default="0" any="0" invert="0" >error</inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="209.129299277862" c2y="68.06747382236853" c1y="62.20534702476807" description="" straight="0" type="2" ypos="121.0319616511284" endx="509.7459371579465" xpos="194.4012784660451" endy="57.68874142396081" c2x="454.6032572476254" >
+    <transition c1x="255.1248961382186" c2y="20.28227680156969" c1y="22.16686619119555" description="" straight="0" type="2" ypos="44.59791675262621" endx="433.4814392114328" xpos="176.7927630221691" endy="40.21480297920117" c2x="370.0846964590581" >
       <from>4</from>
       <to>1</to>
       <inputs default="0" any="0" invert="0" ></inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="479.7764513166009" c2y="139.1101486146292" c1y="136.0848867160959" description="" straight="0" type="2" ypos="142.7712200115032" endx="516.7157287525381" xpos="458.5079188039063" endy="160.7157287525381" c2x="500.3338028272281" >
+    <transition c1x="403.7764513166009" c2y="144.1101486146292" c1y="141.0848867160959" description="" straight="0" type="2" ypos="147.7712200115032" endx="440.7157287525381" xpos="382.5079188039063" endy="165.7157287525381" c2x="424.3338028272281" >
       <from>5</from>
       <to>11</to>
       <inputs default="0" any="0" invert="0" ></inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="617.8976762910015" c2y="136.1406945598321" c1y="99.4683149606862" description="" straight="0" type="2" ypos="131.7652476222788" endx="555.6008762626344" xpos="629.012198097823" endy="85.27119402361126" c2x="554.3592952686665" >
+    <transition c1x="541.8976762910015" c2y="141.1406945598321" c1y="104.4683149606862" description="" straight="0" type="2" ypos="136.7652476222788" endx="479.6008762626344" xpos="553.012198097823" endy="90.27119402361126" c2x="478.3592952686665" >
       <from>6</from>
       <to>1</to>
       <inputs default="0" any="0" invert="0" ></inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="694.4009969792224" c2y="109.1466739985061" c1y="106.5527279954181" description="" straight="0" type="2" ypos="104.4012784660451" endx="572.987801902177" xpos="743.0319616511284" endy="77.23475237772121" c2x="616.7521027550378" >
+    <transition c1x="618.4009969792224" c2y="114.1466739985061" c1y="111.5527279954181" description="" straight="0" type="2" ypos="109.4012784660451" endx="496.987801902177" xpos="667.0319616511284" endy="82.23475237772121" c2x="540.7521027550378" >
       <from>7</from>
       <to>1</to>
       <inputs default="0" any="0" invert="0" ></inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="663.1012667566944" c2y="104.6462720568126" c1y="214.0711292722736" description="" straight="1" type="2" ypos="207.0690002745621" endx="761.422135465079" xpos="744.8208008785988" endy="185.3192078164334" c2x="746.6238415236645" >
+    <transition c1x="587.1012667566944" c2y="109.6462720568126" c1y="219.0711292722736" description="" straight="1" type="2" ypos="212.0690002745621" endx="685.422135465079" xpos="668.8208008785988" endy="190.3192078164334" c2x="670.6238415236645" >
       <from>8</from>
       <to>8</to>
       <inputs default="0" any="0" invert="0" ></inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="836.4502195124187" c2y="154.1920450841325" c1y="185.6912837260082" description="" straight="0" type="2" ypos="200.6542832091899" endx="806.345441926103" xpos="818.5448262821945" endy="138.4806148537085" c2x="814.0679676732817" >
+    <transition c1x="760.4502195124187" c2y="159.1920450841325" c1y="190.6912837260082" description="" straight="0" type="2" ypos="205.6542832091899" endx="730.345441926103" xpos="742.5448262821946" endy="143.4806148537085" c2x="738.0679676732817" >
       <from>8</from>
       <to>7</to>
       <inputs default="0" any="0" invert="0" >start</inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="332.2936058327708" c2y="84.64311455656585" c1y="75.90406924032555" description="" straight="0" type="2" ypos="122.0778968606845" endx="514.9009690243297" xpos="309.5048685537928" endy="68.46005673349059" c2x="455.8448531516539" >
+    <transition c1x="228.2936058327708" c2y="49.45636925733534" c1y="66.90406924032556" description="" straight="0" type="2" ypos="127.0778968606845" endx="432.2906487186517" xpos="233.5048685537928" endy="55.81325470076949" c2x="354.1355018703056" >
       <from>9</from>
       <to>1</to>
       <inputs default="0" any="0" invert="0" ></inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="981.1766461380784" c2y="52.04527950071929" c1y="-2.699689142861658" description="" straight="0" type="2" ypos="140.1985123916005" endx="586.9756478277848" xpos="998.9801487608399" endy="54.99438026795034" c2x="773.573896516404" >
+    <transition c1x="905.1766461380784" c2y="57.04527950071929" c1y="2.300310857138342" description="" straight="0" type="2" ypos="145.1985123916005" endx="510.9756478277848" xpos="922.9801487608399" endy="59.99438026795034" c2x="697.573896516404" >
       <from>10</from>
       <to>1</to>
       <inputs default="0" any="0" invert="0" ></inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="594.9154674167402" c2y="227.8022000533104" c1y="230.1671749801823" description="" straight="0" type="2" ypos="214.5027085613691" endx="640.6871952905944" xpos="575.8157728449876" endy="200.7196133433156" c2x="630.2824046413247" >
+    <transition c1x="518.9154674167402" c2y="232.8022000533104" c1y="235.1671749801823" description="" straight="0" type="2" ypos="219.5027085613691" endx="564.6871952905945" xpos="499.8157728449876" endy="205.7196133433156" c2x="554.2824046413247" >
       <from>11</from>
       <to>6</to>
       <inputs default="0" any="0" invert="0" ></inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="518.7373385402753" c2y="105.3221315444337" c1y="111.8321396520201" description="" straight="0" type="2" ypos="149.7767729723632" endx="523.012198097823" xpos="537.1553545944727" endy="77.23475237772121" c2x="503.7250986549772" >
+    <transition c1x="442.7373385402754" c2y="110.3221315444337" c1y="116.8321396520201" description="" straight="0" type="2" ypos="154.7767729723632" endx="447.012198097823" xpos="461.1553545944727" endy="82.23475237772121" c2x="427.7250986549772" >
       <from>11</from>
       <to>1</to>
       <inputs default="0" any="0" invert="0" >idle</inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="913.2577232722966" c2y="350.6877699588258" c1y="385.9125144071816" description="" straight="0" type="2" ypos="306.6887414239608" endx="510.3702640946119" xpos="1126.745937157946" endy="328.0316549382387" c2x="531.2468427297413" >
+    <transition c1x="837.2577232722966" c2y="355.6877699588258" c1y="390.9125144071816" description="" straight="0" type="2" ypos="311.6887414239608" endx="434.3702640946119" xpos="1050.745937157946" endy="333.0316549382387" c2x="455.2468427297413" >
       <from>12</from>
       <to>3</to>
       <inputs default="0" any="0" invert="0" ></inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="1076.155254591801" c2y="30.07537578006965" c1y="-18.37463333384099" description="" straight="0" type="2" ypos="136" endx="587.639697216413" xpos="1094.000001290323" endy="40.6432841599442" c2x="770.5558088664668" >
+    <transition c1x="1000.155254591801" c2y="35.07537578006965" c1y="-13.37463333384099" description="" straight="0" type="2" ypos="141" endx="511.639697216413" xpos="1018.000001290323" endy="45.6432841599442" c2x="694.5558088664668" >
       <from>13</from>
       <to>1</to>
       <inputs default="0" any="0" invert="0" ></inputs>
       <outputs></outputs>
     </transition>
-    <transition c1x="876.8741592733666" c2y="92.41508378093997" c1y="-4.535631410367188" description="" straight="0" type="2" ypos="139.2446506130552" endx="582.863021484982" xpos="886.5827389570061" endy="65.61044958530236" c2x="680.5772209006713" >
+    <transition c1x="800.8741592733666" c2y="97.41508378093997" c1y="0.4643685896328123" description="" straight="0" type="2" ypos="144.2446506130552" endx="506.863021484982" xpos="810.5827389570061" endy="70.61044958530236" c2x="604.5772209006713" >
       <from>14</from>
       <to>1</to>
       <inputs default="0" any="0" invert="0" ></inputs>
index cd3d9a5..fbe9298 100644 (file)
@@ -25,9 +25,6 @@ package sd_commands_p is
   constant cmd_read_single_block_c : std_logic_cmd_t := to_cmd(cmd_type_std_c, 17);
   constant pad_read_single_block_c : std_logic_vector(31 - block_address_width_c downto 0) := (others => '0');
   
-  constant cmd_do_reset_c : std_logic_cmd_t := to_cmd(cmd_type_int_c, 0);
-  constant arg_do_reset_c : std_logic_arg_t := to_arg(50); -- 1+ ms: 8 SCK (1 byte) @ 400 kHz = 2.5 us * 8 = 20 us
-  
   constant cmd_do_start_c : std_logic_cmd_t := to_cmd(cmd_type_int_c, 1);
   constant arg_do_start_c : std_logic_arg_t := to_arg(10); -- 75+ SCKs (10 byte)
   
index e49a7ef..692d060 100644 (file)
@@ -25,18 +25,19 @@ entity sd_flow_e is
     clock : in std_logic;
     reset : in std_logic;
     
+    init    : in  std_logic;
+    ready   : out std_logic;
+    
     address : in std_logic_block_address_t;
     start   : in std_logic;
     
-    ready : out std_logic;
-    busy  : out std_logic;
-    
     command  : out std_logic_cmd_t;
     argument : out std_logic_arg_t;
     trigger  : out std_logic;
     shifting : in  std_logic;
     error    : in  std_logic;
-    idled    : in  std_logic);
+    idled    : in  std_logic;
+    resetted : out std_logic);
 end sd_flow_e;
 
 -----------------------------------------------------------------------
@@ -62,6 +63,8 @@ architecture rtl of sd_flow_e is
   signal prev_state_s : state_t;
   signal next_state_s : state_t;
 begin
+  resetted <= '1' when curr_state_s = rset_state_c
+         else '0';
   
   sequence : process(clock, reset)
   begin
@@ -69,7 +72,7 @@ begin
       curr_state_s <= rset_state_c;
     elsif rising_edge(clock) then
       case curr_state_s is
-        when rset_state_c => curr_state_s <= send_state_c;
+        when rset_state_c => curr_state_s <= next_state_s;
         when strt_state_c => curr_state_s <= send_state_c;
         when idle_state_c => curr_state_s <= send_state_c;
         when init_state_c => curr_state_s <= loop_state_c;
@@ -96,9 +99,6 @@ begin
     elsif rising_edge(clock) then
       prev_state_s <= curr_state_s;
       case curr_state_s is
-        when rset_state_c =>
-          command  <= cmd_do_reset_c;
-          argument <= arg_do_reset_c;
         when strt_state_c =>
           command  <= cmd_do_start_c;
           argument <= arg_do_start_c;
@@ -130,13 +130,16 @@ begin
   end process;
   
   ready   <= '1' when curr_state_s = wait_state_c else '0';
-  busy    <= '0' when curr_state_s = wait_state_c else '1'; -- TODO?
   trigger <= '1' when curr_state_s = send_state_c else '0';
   
   branch : process(clock)
   begin
     if rising_edge(clock) then
       case curr_state_s is
+        when rset_state_c =>
+          if init = '1' then
+            next_state_s <= strt_state_c;
+          end if;
         when send_state_c =>
           next_state_s <= shft_state_c;
         when shft_state_c =>
@@ -146,7 +149,6 @@ begin
         when vrfy_state_c =>
           if error = '0' then
             case prev_state_s is
-              when rset_state_c => next_state_s <= strt_state_c;
               when strt_state_c => next_state_s <= idle_state_c;
               when idle_state_c => next_state_s <= init_state_c;
               when init_state_c => next_state_s <= init_state_c;
index 152e586..15fc669 100644 (file)
@@ -28,8 +28,8 @@ entity sd_host is
     clk : in  std_logic;
     rst : in  std_logic;
 
+    init  : in  std_logic;
     ready : out std_logic;
-    busy  : out std_logic;
     error : out std_logic;
     
     address : in  std_logic_block_address_t;
@@ -52,18 +52,19 @@ architecture rtl of sd_host is
       clock : in std_logic;
       reset : in std_logic;
     
+      init    : in  std_logic;
+      ready   : out std_logic;
+      
       address : in std_logic_block_address_t;
       start   : in std_logic;
-      
-      ready : out std_logic;
-      busy  : out std_logic;
     
       command  : out std_logic_cmd_t;
       argument : out std_logic_arg_t;
       trigger  : out std_logic;
       shifting : in  std_logic;
       error    : in  std_logic;
-      idled    : in  std_logic);
+      idled    : in  std_logic;
+      resetted : out std_logic);
   end component;
   
   component sd_parser_e is
@@ -83,8 +84,7 @@ architecture rtl of sd_host is
       spi_start : out std_logic;
       spi_busy  : in  std_logic;
       spi_txd   : out std_logic_byte_t;
-      spi_rxd   : in  std_logic_byte_t;
-      spi_cs    : out std_logic);
+      spi_rxd   : in  std_logic_byte_t);
   end component;
 
   component spi_master 
@@ -128,18 +128,19 @@ begin
     clock => clk,
     reset => rst,
     
+    init    => init,
+    ready => ready,
+    
     address => address,
     start   => start,
     
-    ready => ready,
-    busy  => busy,
-    
     command  => sd_command_s,
     argument => sd_argument_s,
     trigger  => sd_trigger_s,
     shifting => sd_shifting_s,
     error    => sd_error_s,
-    idled    => sd_idled_s);
+    idled    => sd_idled_s,
+    resetted => spi_cs_s);
   
   parser : sd_parser_e port map(
     clock => clk,
@@ -157,10 +158,9 @@ begin
     spi_start => spi_start_s,
     spi_busy  => spi_busy_s,
     spi_txd   => spi_txd_s,
-    spi_rxd   => spi_rxd_s,
-    spi_cs    => spi_cs_s);
+    spi_rxd   => spi_rxd_s);
   
-  cs <= not spi_cs_s;
+  cs <= spi_cs_s;
   spi : spi_master port map(
     clk => clk,
     rst => rst,
index be4a4bd..f5d9865 100644 (file)
@@ -37,8 +37,7 @@ entity sd_parser_e is
     spi_start : out std_logic;
     spi_busy  : in  std_logic;
     spi_txd   : out std_logic_byte_t;
-    spi_rxd   : in  std_logic_byte_t;
-    spi_cs    : out std_logic);
+    spi_rxd   : in  std_logic_byte_t);
 end sd_parser_e;
 
 -----------------------------------------------------------------------
@@ -129,7 +128,7 @@ begin
     if reset = '1' then
       error_s <= '0';
     elsif rising_edge(clock) then
-      if state_s = loop_state_c and done_s = '1' then
+      if state_s = vrfy_state_c and (done_s or break_s) = '1' then
         if break_s = '1' then
           if get_cmd_type(command) = cmd_type_std_c then
             error_s <= spi_rxd(6)
@@ -156,24 +155,6 @@ begin
     end if;
   end process;
   
-  selector : process(clock, reset)
-  begin
-    if reset = '1' then
-      spi_cs <= '0';
-    elsif rising_edge(clock) then
-      case state_s is
-        when idle_state_c =>
-          spi_cs <= not error_s;
-        when load_state_c =>
-          if not command = cmd_do_reset_c then
-            spi_cs <= '1';
-          end if;
-        when others =>
-          null;
-      end case;
-    end if;
-  end process;
-  
   sequence : process(clock, reset)
   begin
     if reset = '1' then
index 5729445..5b0cec5 100644 (file)
@@ -29,49 +29,52 @@ architecture test of sd_flow_t is
       clock : in std_logic;
       reset : in std_logic;
     
+      init    : in  std_logic;
+      ready   : out std_logic;
+    
       address : in std_logic_block_address_t;
       start   : in std_logic;
-      
-      ready : out std_logic;
-      busy  : out std_logic;
     
       command  : out std_logic_cmd_t;
       argument : out std_logic_arg_t;
       trigger  : out std_logic;
       shifting : in  std_logic;
       error    : in  std_logic;
-      idled    : in  std_logic);
+      idled    : in  std_logic;
+      resetted : out std_logic);
   end component;
 
   signal test_s : integer;
   
   signal clock_s  : std_logic;
   signal reset_s  : std_logic;
-  
+
+  signal init_i_s     : std_logic;
+  signal ready_o_s    : std_logic;  
   signal address_i_s  : std_logic_block_address_t;
   signal start_i_s    : std_logic;
-  signal ready_o_s    : std_logic;
-  signal busy_o_s     : std_logic;
   signal command_o_s  : std_logic_cmd_t;
   signal argument_o_s : std_logic_arg_t;
   signal trigger_o_s  : std_logic;
   signal shifting_i_s : std_logic;
   signal error_i_s    : std_logic;
   signal idled_i_s    : std_logic;
+  signal resetted_o_s : std_logic;
   
   signal response_sent_s : std_logic;
 begin
   dut : sd_flow_e port map(clock_s, reset_s,
-                       address_i_s,
-                       start_i_s,
-                       ready_o_s,
-                       busy_o_s,
-                       command_o_s,
-                       argument_o_s,
-                       trigger_o_s,
-                       shifting_i_s,
-                       error_i_s,
-                       idled_i_s);
+    init_i_s,
+    ready_o_s,
+    address_i_s,
+    start_i_s,
+    command_o_s,
+    argument_o_s,
+    trigger_o_s,
+    shifting_i_s,
+    error_i_s,
+    idled_i_s,
+    resetted_o_s);
   
   response : process
     procedure respond(
@@ -79,8 +82,8 @@ begin
       idled : std_logic) is
     begin
       wait until rising_edge(trigger_o_s);
-      error_i_s <= 'U';
-      idled_i_s <= 'U';
+      error_i_s <= '0';
+      idled_i_s <= '0';
       wait until rising_edge(clock_s);
       wait until rising_edge(clock_s);
       wait until rising_edge(clock_s);
@@ -97,13 +100,12 @@ begin
     end respond;
     procedure respond_init is
     begin
-      respond('0', '0');   -- rset
-      respond('0', '0');   -- strt
+      respond('0', '0'); -- strt
       respond('0', '1'); -- idle
       respond('0', '1'); -- init
       respond('0', '1'); -- init
-      respond('0', '0');   -- init
-      respond('0', '0');   -- bsiz
+      respond('0', '0'); -- init
+      respond('0', '0'); -- bsiz
     end;
   begin
     response_sent_s <= '0';
@@ -130,6 +132,20 @@ begin
              else '0' when response_sent_s = '1'
              else unaffected;
   
+  initializer : process
+  begin
+    init_i_s <= '0';
+    wait until falling_edge(reset_s);
+    
+    while true loop
+      wait until rising_edge(clock_s);
+      init_i_s <= '1';
+      wait until rising_edge(clock_s);
+      init_i_s <= '0';
+      wait until rising_edge(resetted_o_s);
+    end loop;
+  end process;
+  
   starter : process
   begin
     address_i_s <= (others => 'U');
@@ -154,8 +170,10 @@ begin
     wait until falling_edge(reset_s);
     test_s <= test_s + 1;
     while true loop
-      wait until rising_edge(start_i_s);
-      test_s <= test_s + 1;
+      if (init_i_s or start_i_s) = '1' then
+        test_s <= test_s + 1;
+      end if;
+      wait until rising_edge(clock_s);
     end loop;
   end process;
   
index c77731d..ceeb567 100644 (file)
@@ -45,8 +45,7 @@ architecture test of sd_parser_t is
       spi_start : out std_logic;
       spi_busy  : in  std_logic;
       spi_txd   : out std_logic_byte_t;
-      spi_rxd   : in  std_logic_byte_t;
-      spi_cs    : out std_logic);
+      spi_rxd   : in  std_logic_byte_t);
   end component;
 
   signal test_s : integer;
@@ -65,7 +64,6 @@ architecture test of sd_parser_t is
   signal busy_i_s     : std_logic;
   signal txd_o_s      : std_logic_byte_t;
   signal rxd_i_s      : std_logic_byte_t;
-  signal cs_o_s       : std_logic;
   
   constant address_c  : std_logic_block_address_t := "10101010101010101010101";
   
@@ -84,8 +82,7 @@ begin
     start_o_s,
     busy_i_s,
     txd_o_s,
-    rxd_i_s,
-    cs_o_s);
+    rxd_i_s);
   
   stimulus : process
     procedure send(